About Me
Welcome! I am a third-year Ph.D. student in Electrical Engineering at the University of Minnesota, advised by Prof. Yang Zhao. My research interests lie at the intersection of computer architecture and emerging AI worloads, with a particular focus on Hardware–Algorithm Co-design for Efficient AI and AI-assisted hardware design. Before joining UMN, I received my B.Eng. degree in Microelectronics Science and Engineering from Fudan University, where I worked with Prof. Lingli Wang on reconfigurable accelerator designs.
Research Interests
Algorithm-Hardware Co-Design for Emerging Workloads
I develop efficient computing architectures for emerging AI workloads and pipelines, including Vision-Language-Action (VLA) models, Reinforcement Learning, Mixture-of-Experts (MoE), and 3D Gaussian Splatting SLAM (3DGS-SLAM). My work spans specialized accelerators, chiplet and wafer-scale systems, and GPU server-edge co-design to improve the performance and efficiency of AI systems.
Automatic AI Agent Systems for Hardware Design
I explore LLM- and multi-agent-based systems for automated hardware design, with applications in RTL generation, chiplet design, hardware debugging, and RISC-V instruction extension. My research aims to make complex hardware design more scalable and automated while reducing human effort.
Education
University of Minnesota
Ph.D. in Electrical Engineering
Sep 2024 – Present
Fudan University
B.E. in Microelectronic Science and Engineering
Sep 2020 – Jun 2024
Selected Publications
* Equal contribution.
RTGS: Real-Time 3D Gaussian Splatting SLAM via Multi-Level Redundancy Reduction
Authors: Leshu Li*, Jiayin Qin*, Jie Peng, Zishen Wan, Huaizhi Qu, Ye Han, Pingqing Zheng, Hongsen Zhang, Yu Cao, Tianlong Chen, Yang Zhao
International Symposium on Microarchitecture (MICRO), 2025
Mozart: Modularized and Efficient MoE Training on 3.5D Wafer-Scale Chiplet Architectures
Authors: Shuqing Luo*, Ye Han*, Pingzhi Li*, Jiayin Qin*, Jie Peng, Yang Zhao, Yu Cao, Tianlong Chen
Annual Conference on Neural Information Processing Systems (NeurIPS), 2025, Spotlight
HDLxGraph: Bridging Large Language Models and HDL Repositories via HDL Graph Databases
Authors: Pingqing Zheng, Jiayin Qin, Fuqi Zhang, Niraj Chitla, Zishen Wan, Shang Wu, Yu Cao, Caiwen Ding, Yang Zhao
Asia and South Pacific Design Automation Conference (ASP-DAC), 2026
MAHL: Multi-Agent LLM-Guided Hierarchical Chiplet Design with Adaptive Debugging
Authors: Jinwei Tang*, Jiayin Qin*, Nuo Xu, Pragnya Sudershan Nalla, Yu Cao, Yang Zhao, Caiwen Ding
IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2025
HiVeGen: Hierarchical LLM-based Verilog Generation for Scalable Chip Design
Authors: Jinwei Tang*, Jiayin Qin*, Kiran Thorat, Chen Zhu-Tian, Yu Cao, Yang Zhao, Caiwen Ding
IEEE International Conference on LLM-Aided Design (ICLAD), 2025, Best Paper Award
LACE: Large Language Model Aided Multi-Agent Framework for Agile RISC-V Instruction Extension
Authors: Pingqing Zheng, Jiayin Qin, Fuqi Zhang, Zishen Wan, Shang Wu, Yu Cao, Caiwen Ding, Yang Zhao
IEEE International Conference on LLM-Aided Design (ICLAD), 2026
CGRA-HD: An Efficient Reconfigurable Accelerator for Hyperdimensional Computing
Authors: Jiayin Qin*, Yuan Dai*, Lingli Wang
International Conference on Field-Programmable Technology (FPT), 2024